Skip to content
@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

Pinned Loading

  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 960

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 445 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 188 111

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 76

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 146

Repositories

Showing 10 of 110 repositories
  • XiangShan-Dashboard Public
    OpenXiangShan/XiangShan-Dashboard's past year of commit activity
    Vue 2 0 0 3 Updated Oct 13, 2026
  • XiangShan-Design-Doc Public

    Documentation for XiangShan Design

    OpenXiangShan/XiangShan-Design-Doc's past year of commit activity
    Markdown 52 CC-BY-4.0 17 5 7 Updated Oct 13, 2026
  • bootcamp Public

    XiangShan bootcamp

    OpenXiangShan/bootcamp's past year of commit activity
    Jupyter Notebook 7 CC-BY-4.0 4 0 0 Updated Oct 13, 2026
  • minjie-playground Public

    MinJie is an open-source platform supporting agile hardware development flow. This is a playground for the MinJie agile chip design tools.

    OpenXiangShan/minjie-playground's past year of commit activity
    Python 10 MulanPSL-2.0 4 0 4 Updated Oct 13, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,306 MulanPSL-2.0 960 142 179 Updated Oct 13, 2026
  • XSAICache Public Forked from OpenXiangShan/XSCache

    A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.

    OpenXiangShan/XSAICache's past year of commit activity
    Scala 1 8 0 2 Updated Oct 13, 2026
  • gsim Public
    OpenXiangShan/gsim's past year of commit activity
    C++ 86 13 2 9 Updated Oct 13, 2026
  • difftest Public

    Modern co-simulation framework for RISC-V CPUs

    OpenXiangShan/difftest's past year of commit activity
    C++ 188 MulanPSL-2.0 111 8 15 Updated Oct 13, 2026
  • XiangShanLab Public

    XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

    OpenXiangShan/XiangShanLab's past year of commit activity
    Scala 49 25 53 4 Updated Oct 13, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 146 40 47 Updated Oct 13, 2026
View all repositories

Most used topics

chisel risc-v