📌Featured Projects
Argo: RISCV SoC with a systolic array accelerator
Argo is a small AI-accelerator SoC built around a PicoRV32 RISC-V core, an 8x8 systolic array for matrix multiply, two 4 KB SRAM macros, SPI boot and UART, all inside a full IO ring with bond pads. I took it from RTL to GDS on IHP’s SG13CMOS5L 130nm process with LibreLane, OpenROAD and Yosys, and signed it off entirely in KLayout: zero DRC, density and antenna errors, a matching LVS, and gate-level simulation passing on the routed netlist. It runs at 100 MHz at the typical corner and is planned for fabrication through IHP.
Custom ISA accelerator
RV32I pipeline with custom RISC-V ISA extension (MLOAD/MMUL/MSTORE) offloading 8x8 matrix multiply to a weight-stationary systolic array over AXI-Lite. 27/27 tests passing, ASAP7 7nm PD: 11,562 cells, 1,515 µm², 756MHz.
2 Warp SIMT GPU Core — RTL to GDS
2-warp, 8-lane SIMT execution engine in RV32I. Round-robin warp scheduler with load stall detection, per-lane register files, and 8-bank scratchpad memory. Verified with a directed testbench (34/34 passing) and Spike ISS co-simulation across all 8 lanes.
Full RTL-to-GDS on ASAP7 via OpenROAD: 663 cells, 2,862.66 µm² core area, 500 MHz, 0 DRC violations. 8x fakeram7_256x32 SRAM macros visible on the right (2,808.96 µm², ~98% of die area), standard cell logic on the left (~54 µm²).
PicoRISCV-SoC — RISC-V SoC with ML Accelerator
PicoRV32 (RV32IM) CPU integrated with an 8x8 weight-stationary systolic array over AXI-Lite MMIO and a 4-wire SPI slave interface (390 to 4 pins).
Full RTL-to-GDS on ASAP7 via OpenROAD: 47,051 cells, 5,431 µm², 500 MHz, 0 DRC violations. IRQ feedback from accelerator to CPU on computation complete.
Systolic Array Accelerator — RTL to GDS
8x8 weight-stationary systolic array, INT8 weights, INT32 accumulators. Full OpenROAD flow on two nodes:
10x frequency, 67.1x area reduction across nodes. Submitted to ChipFoundry CI2609 shuttle via Caravel wrapper.
UVM-Style Systolic Array Testbench
Structured SystemVerilog testbench for the 8x8 systolic array, built without a UVM library to run cleanly under Verilator 5.020. Per-PE scheduled checks using a timing model, constrained random stimulus, and 5 SVA properties checking protocol correctness every clock cycle.
1,337 functional checks, zero failures across 5 random seeds 15/15 functional coverage bins closed Resolved a Verilator --timing coroutine limitation where post-NBA signal values are invisible inside tasks by moving psum checks into a dedicated always block
RV32I 5-Stage Pipelined CPU
Full RV32I pipeline in SystemVerilog with forwarding, load-use stall detection, branch resolution, and a 2-bit saturating counter branch predictor. 27/27 directed tests passing across ALU ops, RAW hazard chains, load-use hazards, branches, JAL, LUI, and SLTU.
Reran the testbench under Synopsys VCS: 26/27 checks passed identically to Verilator.
ML-Based Physical Design Automation
Random Forest regression model predicting post-synthesis PPA from RTL features, achieving 92% accuracy. Automated via Python and TCL scripts integrated into the OpenROAD flow, cutting manual iteration cycles by 40%.
Arya-OS
A bare-metal x86 kernel built from scratch in C and x86 assembly with a bootloader through preemptive multitasking, with no OS underneath. I built as a systems-level counterpart to hardware/RTL work: a way to understand the hardware/software boundary from the software side, one layer at a time.
