cpu-gpu

[ISCA'25] LIA: A Single-GPU LLM Inference Acceleration with Cooperative AMX-Enabled CPU-GPU Computation and CXL Offloading

Evidence-driven PresentMon diagnostics and policy modeling paired with bounded owned-lab D3D11 runtime actuation.

Turing-Complete 16-Bit CPU — 32-Instruction ISA, 20-Bit Address Bus & 32-Level Call Stack — Designed by a 12-Year-Old in One Week

Exploring CPU/GPU memory hierarchies, cache modeling, DRAM simulation, GPU programming with CUDA, and near-data processing using PIMeval-PIMbench - CS 6501 CPU/GPU Memory Systems @ UVA Spring '25

Seed-controlled discrete-event model of CPU-side scheduling in a CPU-GPU pipeline; companion code for the ISPDS 2026 paper on GPU queue feedback

CPU/GPU/MEMORY monitor (2023)

From-scratch finite element analysis (fea_engine) and reduced-order modeling (rom_engine) in Python: NumPy/SciPy core with optional PyTorch/GPU, linear and nonlinear solvers, POD/Galerkin, balanced truncation, nonlinear structural ROMs, and validated examples.

Multi-Channel Radio Astronomical Data Gridding Framework